Registered Layout-Designs of Integrated Circuits Ordinance, 2000

This 2000 Ordinance creates a system for legally protecting the "layout-designs" of integrated circuits (computer chips) -- essentially the three-dimensional arrangement of the electronic elements and connections that make up a chip. It was passed to meet Pakistan's obligations under the WTO's TRIPS agreement on intellectual property (preamble).

Section 3 requires a layout-design to be "original" -- the result of the creator's own intellectual effort, not commonplace among other designers at the time it was made -- to qualify for protection. Section 4 gives the right to protection to the design's creator, or jointly to multiple creators, or to an employer/commissioning party if the design was made under a job or contract (unless otherwise agreed). Section 5 spells out what counts as infringement: reproducing a registered design (in whole or in significant part) or importing, selling, or distributing it commercially without the right-holder's authorization. The same section carves out exceptions for private use, research, teaching, and reverse-engineering that leads to a genuinely new original design.

Section 6 sets the length of protection: it starts on the date the design is first commercially exploited anywhere in the world and lasts until the end of the tenth calendar year after that date. Sections 7-9 describe the registration process -- applications go to the Patent Office and are examined by the Controller of Patents, who maintains a public Register of Layout-Designs. Section 10 lets someone whose design was copied without consent apply to have a wrongly-filed application or registration transferred to them, and Section 13 allows any interested person to apply to the District Court to have a registration cancelled if the design wasn't actually original or eligible.

Section 15 lets a right-holder sue in the District Court for an injunction and damages against infringement. Section 16 sets out the criminal penalty: knowingly infringing a registered layout-design is an offence punishable with imprisonment for up to two years, a fine of not less than two hundred thousand rupees, or both, and the court can also order seizure and destruction of the infringing chips and the equipment used to make them. Section 17 allows the Federal Government, in the public interest (such as national security or health) or where a design is being used anti-competitively, to authorise a government agency or third party to exploit a registered design even without the right-holder's consent, subject to paying fair compensation. Appeals from Controller and District Court decisions go to the High Court (Section 19).